H8S2138 Datasheet, PDF (219/1061 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 7 Data Transfer Controller [H8S/2138 Group]
7.2.3 DTC Source Address Register (SAR)
Bit
23 22 21 20 19
43210
Initial value
Read/write
Unde- Unde- Unde-Unde- Unde-
fined fined fined fined fined
—————
Unde- Unde-Unde- Unde-Unde-
fined fined fined fined fined
—————
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
7.2.4 DTC Destination Address Register (DAR)
Bit
23 22 21 20 19
43210
Initial value
Read/write
Unde- Unde- Unde-Unde- Unde-
fined fined fined fined fined
—————
Unde- Unde-Unde- Unde-Unde-
fined fined fined fined fined
—————
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
7.2.5 DTC Transfer Count Register A (CRA)
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value
Read/Write
Unde- Unde- Unde-Unde- Unde-Unde- Unde-Unde- Unde-Unde- Unde-Unde- Unde-Unde- Unde-Unde-
fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
————————————————
CRAH
CRAL
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA register functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, CRA is divided into two parts: the upper 8 bits (CRAH)
and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-
bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the
contents of CRAH are transferred when the count reaches H'00. This operation is repeated.
Rev. 4.00 Jun 06, 2006 page 165 of 1004
REJ09B0301-0400