H8S2556 Datasheet, PDF (970/982 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2500 Series

Item
Page Revision (See Manual for Details)
13.3.9 Bit Rate Register 424
(BRR)
Table 13.3 BRR Settings
for Various Bit Rates
(Asynchronous Mode)
Table 13.3 amended
Operating Frequency φ (MHz)
25
Bit Rate
(bps)
nN
Error
(%)
110
3 110 –0.02
150
3 80
0.47
300
2 162 –0.15
600
2 80
0.47
1200
2400
4800
1 162 –0.15
1 80
0.47
0 162 –0.15
9600
19200
0 80
0 40
0.47
–0.76
31250
38400
0 24 0.00
0 19 1.73
14.3.1 I²C Bus Control
Register (ICCR1)
14.3.5 I²C Bus Status
Register (ICSR)
484 RCVD description amended
This bit enables or disables the next receive operation while
TRS is 0 and until ICDRR is read.
493 STOP description amended
[Setting condition]
• In master mode, when a stop condition is detected after
frame transfer
• In slave mode, when a stop condition is detected after the
general call address or the first byte slave address, next to
detection of start condition, accords with the address set in
SAR
14.4.3 Master Receive
Operation
499 Description amended
4. The continuous reception…every time RDRF is set. If,
while RDRF is set to 1, the reading of ICDRR is delayed by
other processing and does not occur by the falling edge of the
8th clock pulse, set RDVD to 1 and perform one-byte data
transfer.
5. If next frame is the last receive data, ...
14.4.6 Clocked
507
Synchronous Serial Format
Figure 14.15 Receive
Mode Operation Timing
Figure 14.15 amended
SCL
1
2
SDA
(Input)
Bit 0 Bit 1
7
8
1
Bit 6 Bit 7 Bit 0
7
8
1
2
Bit 6 Bit 7 Bit 0 Bit 1
Rev.5.00 Sep. 27, 2007 Page 924 of 932
REJ09B0099-0500