H8S2556 Datasheet, PDF (425/982 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2500 Series

Section 12 Watchdog Timer (WDT)
Section 12 Watchdog Timer (WDT)
The watchdog timer (WDT) is an 8-bit timer in two channels that can reset this LSI internally or
generate the internal NMI interrupt, if a system crash prevents the CPU from writing to the timer.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
The block diagram of the WDT is shown in figure 12.1.
12.1 Features
• Selectable from eight counter input clocks for WDT_0
Selectable from 16 counter input clocks for WDT_1
• Switchable between watchdog timer mode and interval timer mode
Watchdog timer mode
• If the counter in WDT_0 overflows, it is possible to select whether this LSI is internally reset
or not
• Power-on reset and manual reset are selectable for internal reset
• If the counter in WDT_1 overflows, it is possible to select whether this LSI is internally reset
at a power-on timing or the internal NMI interrupt is generated
Interval timer mode
• If the counter overflows, the WDT generates an interval timer interrupt (WOVI)
• Selected clock can be output from BUZZ output pin (WDT_1)
Rev.5.00 Sep. 27, 2007 Page 379 of 932
REJ09B0099-0500