H8S2556 Datasheet, PDF (510/982 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2500 Series

Section 13 Serial Communication Interface (SCI)
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransferred frame
Transfer
frame n+1
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4
RDRF
PER
Figure 13.29 Retransfer Operation in SCI Receive Mode
Start
Initialization
Start reception
ORER = 0 and
No
PER = 0
Yes
No
RDRF = 1?
Yes
Read RDR and clear
RDRF flag in SSR to 0
Error processing
No
All data received?
Yes
Clear RE bit to 0
Figure 13.30 Example of Reception Processing Flow
13.7.8 Clock Output Control
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and
CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width.
Figure 13.31 shows the timing for fixing the clock output level. In this example, GM is set to 1,
CKE1 is cleared to 0, and the CKE0 bit is controlled.
Rev.5.00 Sep. 27, 2007 Page 464 of 932
REJ09B0099-0500