H8S2556 Datasheet, PDF (389/982 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2500 Series

10.9 Usage Notes
Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.1 Module Stop Mode Setting
TPU operation can be disabled or enabled using the module stop control register. The initial
setting is for TPU operation to be halted. Register access is enabled by clearing module stop
mode. For details, see section 22, Power-Down Modes.
10.9.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.44 shows the input clock
conditions in phase counting mode.
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Phase
Phase
differ-
differ-
Overlap _ence Overlap _ence
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width
: 2.5 states or more
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Rev.5.00 Sep. 27, 2007 Page 343 of 932
REJ09B0099-0500