H8S2556 Datasheet, PDF (630/982 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2500 Series

Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
Initial
Bit Bit Name Value R/W Description
3
UE
0
R/W Underrun Error
Indicates that an underrun error has occurred during data
transmission. The IEB detects an underrun error
occurrence when the IEB fetches data from IETBR while
the TxRDY flag is set to 1, and the IEB sets the TxE flag
and enters the wait state. Accordingly, when the TxRDY
flag is not cleared even if data is written to IETBR, an
underrun error occurs and data transmission is
terminated. Note that the TxRDY flag must be cleared in
data transmission by the CPU.
[Setting condition]
• When the IEB loads data from IETBR to the transmit
shift register while the TxRDY flag is set to 1
[Clearing condition]
• When writing 0 after reading UE = 1
2
TTME
0
R/W Timing Error
Set to 1 if data is not transmitted at the timing specified by
the IEBus protocol during data transmission. The IEB sets
the TxE flag and enters the wait state.
[Setting condition]
• When a timing error occurs during data transmission
[Clearing condition]
• When writing 0 after reading TTME = 1
Rev.5.00 Sep. 27, 2007 Page 584 of 932
REJ09B0099-0500