H8S2556 Datasheet, PDF (969/982 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2500 Series

Item
Page Revision (See Manual for Details)
9.13.2 Port F Data
Register (PFDR)
254 PF7DR to PF0DR description amended
Output data for a pin is stored when the pin is specified as a
general purpose output port.
9.14.2 Port G Data
Register (PGDR)
258 PG4DR to PG0DR description amended
Output data for a pin is stored when the pin is specified as a
general purpose output port.
9.15.2 Port H Data
Register (PHDR)
261 PH7DR to PH0DR description amended
Output data for a pin is stored when the pin is specified as a
general purpose output port.
9.16.2 Port J Data
Register (PJDR)
264 PJ7DR to PJ0DR description amended
Output data for a pin is stored when the pin is specified as a
general purpose output port.
9.18 Handling of Unused 267 Section 9.18 added
Pins
10.3.1 Timer Control
Register (TCR)
278 CKEG1 and CKEG0 description amended
This setting is ignored if the input clock isφ/1, or when
overflow/underflow of another channel is selected. (The clock
is counted at the falling edge when φ/1 is selected.)
11.3.5 Timer
Control/Status Register
(TCSR)
362, • TCSR_0
363 _{Note*2 deleted}
(Before) R/(W)*¹ → (After) R/(W)*
OVF [Clearing condition]
(Before) Read OVF when OVF = 1*², then write 0 in OVF →
(After) Read OVF when OVF = 1, then write 0 in OVF
12.6.1 Notes on Register 395 Figure 12.7 amended
Access
Writing 0 to WOVF bit
Figure 12.7 Writing to
RSTCSR
15
87
0
Address: H'FF76
H'A5
H'00
Writing to RSTE or RSTS bit
15
Address: H'FF76
H'5A
87
0
Write data
12.6.3 Changing Value 396 Description amended
of PSS or CKS2 to CKS0
If the PSS or CKS0 to CKS2 bits in TCSR are modified while
the WDT is operating, errors could occur in the incrementation.
Software must be used to stop the watchdog timer (by clearing
the TME bit to 0) before changing the value of the PSS or
CKS0 to CKS2 bits.
Rev.5.00 Sep. 27, 2007 Page 923 of 932
REJ09B0099-0500