H8S2556 Datasheet, PDF (935/982 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2500 Series

Section 24 Electrical Characteristics
Table 24.6 Clock Timing (2)
Conditions
(for H8S/2556 Group):
V_CC = P1V_CC = P2V_CC = 5.0 V ±0.5 V (BUFGC1 and BUFGC2 in ICPCR are 0)/ 3.3 V ±0.3 V
(BUFGC1 and BUFGC2 in ICPCR are 1),
AV_CC = 3.0 V to 5.5 V, V_ref = 3.0 V to AV_CC, V_SS = AV_SS = 0 V, φ= 32.768 kHz,
8 to 20 MHz, Ta = –40°C to +85°C (wide-range specifications)
Item
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
EXTAL clock input PLL1
frequency
multiplication
PLL2
multiplication
Clock oscillator settling time at reset
(crystal)
Clock oscillator settling time at reset
(external clock)
Clock oscillator settling time in
software standby (crystal)
External clock settling delay time
Subclock oscillator settling time
Subclock oscillator frequency
Subclock (φ_SUB) cycle time
Symbol Min.
t_cyc
50
t
18
CH
t_CL
18
t
⎯
Cr
t
⎯
Cf
f
8
EX
8
Max.
125
⎯
⎯
5
5
20
10
t_OSC1
20
⎯
20
⎯
t
OSC2
t
DEXT
t_OSC3
f_SUB
t_SUB
8
⎯
8
⎯
2
⎯
32.768
30.5
Unit
ns
ns
ns
ns
ns
MHz
ms
ms
ms
ms
s
kHz
μs
Test Conditions
Figure 24.5
Figure 21.5
Figure 24.6
Figure 22.3
Figure 24.6
t_cyc
t_CH
t_Cf
φ
t_CL
t_Cr
Figure 24.5 System Clock Timing
Rev.5.00 Sep. 27, 2007 Page 889 of 932
REJ09B0099-0500