M16C30_02 Datasheet, PDF (94/178 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O
Mitsubishi microcomputers
M16C / 30 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O is configured as three channels: UART0, UART1, UART2.
UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate
independently of each other.
Figure 1.16.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.16.2 and 1.16.3 show
the block diagram of the transmit/receive unit.
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses
03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a
UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions.
UART2, in particular, is used for the SIM interface with some extra settings added in clock-asynchronous
serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if
the TxD pin and the RxD pin are different in level.
Table 1.16.1 shows the comparison of functions of UART0 through UART2, and Figures 1.16.4 to 1.16.9
show the registers related to UARTi.
Note: SIM : Subscriber Identity Module
Table 1.16.1. Comparison of functions of UART0 through UART2
Function
UART0
UART1
CLK polarity selection
Possible (Note 1) Possible (Note 1)
UART2
Possible (Note 1)
LSB first / MSB first selection
Possible (Note 1) Possible (Note 1) Possible (Note 2)
Continuous receive mode selection
Transfer clock output from multiple
pins selection
Serial data logic switch
Possible (Note 1) Possible (Note 1) Possible (Note 1)
Impossible
Possible (Note 1) Impossible
Impossible
Impossible
Possible (Note 4)
Sleep mode selection
Possible (Note 3) Possible (Note 3) Impossible
TxD, RxD I/O polarity switch
TxD, RxD port output format
Parity error signal output
Impossible
CMOS output
Impossible
Impossible
CMOS output
Impossible
Possible
N-channel open-drain
output
Possible (Note 4)
Bus collision detection
Impossible
Impossible
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
Possible
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