M16C30_02 Datasheet, PDF (100/178 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O
Mitsubishi microcomputers
M16C / 30 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0(i=0,1)
Address
When reset
03A416, 03AC16
0816
Bit
symbol
CLK0
CLK1
CRS
TXEPT
Bit name
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
RW
BRG count source
select bit
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Must not be set.
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Must not be set.
CTS/RTS function
select bit
Valid when bit 4 = “0”
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1) 0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2) _{1 : RTS function is selected (Note 2)}
Transmit register empty
flag
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
CRD CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
NCH Data output select bit
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
CKPOL CLK polarity select bit
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Must always be “0”
UFORM Transfer format select bit ^{0 : LSB first}
1 : MSB first
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
UART2 transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C0
Address
037C16
When reset
0816
Bit
symbol
Bit name
CLK0
CLK1
BRG count source
select bit
Function
(During clock synchronous
serial I/O mode)
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Must not be set.
Function
(During UART mode)
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Must not be set.
RW
CRS
TXEPT
CTS/RTS function
select bit
Valid when bit 4 = “0”
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1) 0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2) _{1 : RTS function is selected (Note 2)}
Transmit register empty
flag
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
CRD CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions
programmable I/O port)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions programmable
I/O port)
Nothing is assigned.
0 : TXDi pin is CMOS output
0: TXDi pin is CMOS output
In an attempt to write to this bit, write¹â€œ^:0^T”.^XT^Dhⁱ e^pinva^islu^Ne^-,^chif^arⁿeⁿa^ed^l , turns o¹u^:t^Tto^XDbⁱe^pin“0^is”.^N-channel
open-drain output
open-drain output
CKPOL CLK polarity select bit
0 : Transmit data is output at
falling edge of transfer clock
Must always be “0”
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
UFORM ^{Transfer format select bit 0 : LSB first}
(Note 3)
1 : MSB first
0 : LSB first
1 : MSB first
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Figure 1.16.6. Serial I/O-related registers (3)
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