M16C30_02 Datasheet, PDF (29/178 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Bus Control
Mitsubishi microcomputers
M16C / 30 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example 1) After access the external area, both the address signal and
the chip select signal change concurrently in the next cycle.
In this example, after access to the external area(i), an access to the area
indicated by the other chip select signal(j) will occur in the next cycle. In
this case, both the address bus and the chip select signal change between
the two cycles.
Example 2) After access the external area, only the chip select signal
changes in the next cycle (the address bus does not change).
In this example, an access to the internal ROM or the internal RAM in the
next cycle will occur, after access to the external area. In this case, the
chip select signal changes between the two cycles, but the address does
not change.
Access to the Access to the Other
External Area( i ) External Area( j )
BCLK
Read/Write
signal
Data bus
Address bus
Chip select
(CS i)
Chip select
(CS j)
Data
Address
Access to the Internal ROM/RAM
External Area Access
BCLK
Read/Write
signal
Data bus
Address bus
Chip select
Data
Address
Example 3) After access the external area, only the address bus changes
in the next cycle (the chip select signal does not change).
In this example, after access to the external area(i), an access to the area
indicated by the same chip select signal(i) will occur in the next cycle. In
this case, the address bus changes between the two cycles, but the chip
select signal does not change.
Example 4) After access the external area, either the address signal and
the chip select signal do not change in the next cycle.
In this example, any access to any area does not occur in the next cycle
(either instruction prefetch does not occur). In this case,either the address
bus and chip select signal do not change between the two cycles.
Access to the Access to the Same
External Area( i ) External Area( i )
BCLK
Read/Write
signal
Data bus
Address bus
Chip select
(CS i)
Data
Address
Access to the
External Area
No Access
BCLK
Read/Write
signal
Data bus
Address bus
Chip select
Data
Address
Note : These examples show the address bus and chip select signal within the successive two cycles.
According to the combination of these examples, the chip select can be elongated to over 2cycles.
Figure 1.9.2. Output Examples about Address Bus and Chip Select Signal (Separated Bus without
Wait)
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