M16C30_02 Datasheet, PDF (51/178 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupt
Mitsubishi microcomputers
M16C / 30 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt control register (Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
BCNIC
DM0IC
KUPIC
ADIC
SiTIC(i=0 to 2)
SiRIC(i=0 to 2)
TAiIC(i=0 to 2)
TBiIC(i=1, 2)
Address
004A16
004B16
004D16
004E16
005116, 005316, 004F16
005216, 005416, 005016
005516 to 005716
005B16, 005C16
When reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Bit symbol
Bit name
ILVL0
Interrupt priority level
select bit
ILVL1
ILVL2
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
IR
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
(Note 1)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the
interrupt request for that register. For details, see the precautions for interrupts.
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INTiIC(i=0 to 2)
Address
When reset
005D16 to 005F16 XX00X0002
Bit symbol
Bit name
ILVL0
Interrupt priority level
select bit
ILVL1
ILVL2
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
IR
Interrupt request bit
POL
Polarity select bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
(Note 1)
Reserved bit
Must always be set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Figure 1.11.3. Interrupt control registers
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