M16C30_02 Datasheet, PDF (129/178 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register 2
Mitsubishi microcomputers
M16C / 30 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P70 through P72 conforming to the simplified I ²C bus
P70/TxD2/SDA
P71/RxD2/SCL
P72/CLK2
Timer
I/O
Selector
SDDS=0
UART2 _{or DL=000}
Digital delay
(Divider)
SDDS=1 and
DL≠000
IICM=1 (SDDS=0) or
DL=000 (SDDS=1)
UART2
Analog
delay
Transmission
register
IICM=0 or
DL≠000 (SDDS=1)
SDHI
ALS
IICM=0
or IICM2=1
IICM=1
and IICM2=0
UART2 transmission/
NACK interrupt request
Noize
Filter
Noize
Filter
Noize
Filter
DQ
Arbitration
T
Timer
IICM=1
Reception register
IICM=0
or IICM2=1
UART2 reception/ACK interrupt
request
IICM=0
Start condition
detection
Stop condition
UART2
S
Q
R
Bus busy
IICM=1
and IICM2=0
detection
Falling edge
detection
L-synchronous
output enabling
bit
NACK
DQ
T
Selector
I/O
R
Q
Data bus
(Port P71 output data latch)
UART2
Internal clock
DQ
T
ACK
9th pulse
IICM=1
Bus collision/start, stop condition
detection interrupt request
IICM=1
IICM=1
SWC2
CLK
control
Bus collision
detection
External clock
UART2
IICM=0
IICM=0
Falling edge of 9 bit
SWC
UART2
IICM=0
Selector
I/O
Timer
Port reading
* With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7 1 of the direction register.
To DMA0
To DMA0
Figure 1.16.30. Functional block diagram for I²C mode
Functions available in I²C mode are shown in Figure 1.16.30 — a functional block diagram.
Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Setting
this bit to “1” causes an arbitration loss to occur, and the SDA pin turns to high-impedance state at the
instant when the arbitration lost detecting flag is set to “1”.
Bit 1 of the UART2 special mode register 2 (address 037616) is used as the clock synchronization bit.
With this bit set to “1” at the time when the internal SCL is set to “H”, the internal SCL turns to “L” if the
falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting
within the “L” interval. When the internal SCL changes from “L” to “H” with the SCL pin set to “L”, stops
counting the baud rate generator, and starts counting it again when the SCL pin turns to “H”. Due to this
function, the UART2 transmission-reception clock becomes the logical product of the signal flowing
through the internal SCL and that flowing through the SCL pin. This function operates over the period
from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the
ninth bit. To use this function, choose the internal clock for the transfer clock.
Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit to
“1” causes the SCL pin to be fixed to “L” at the falling edge of the ninth bit of the clock. Setting this bit to
“0” frees the output fixed to “L”.
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