H8S2633 Datasheet, PDF (903/1487 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Bit 3
AL
0
1
Section 18 I²C Bus Interface [Option] (This function is not available in the H8S/2695)
Description
Bus arbitration won
(Initial value)
[Clearing conditions]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in AL after reading AL = 1
Arbitration lost
[Setting conditions]
1. If the internal SDA and SDA pin disagree at the rise of SCL in master transmit
mode
2. If the internal SCL line is high at the fall of SCL in master transmit mode
Bit 2—Slave Address Recognition Flag (AAS): In I²C bus format slave receive mode, this flag is
set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the
general call address (H'00) is detected.
AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 2
AAS
0
1
Description
Slave address or general call address not recognized
(Initial value)
[Clearing conditions]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in AAS after reading AAS = 1
3. In master mode
Slave address or general call address recognized
[Setting condition]
When the slave address or general call address is detected in slave receive mode and
FS = 0
Bit 1—General Call Address Recognition Flag (ADZ): In I²C bus format slave receive mode,
this flag is set to 1 if the first frame following a start condition is the general call address (H'00).
Rev. 5.00 Mar 28, 2005 page 841 of 1422
REJ09B0234-0500