H8S2633 Datasheet, PDF (1144/1487 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 26 Electrical Characteristics (H8S/2633R)
26.3.1 Clock Timing
Table 26.5 lists the clock timing
Table 26.5 Clock Timing
Conditions: PV_CC = 4.5 V to 5.5 V, AV_CC = 4.5 V to 5.5 V, V_ref = 4.5 V to AV_CC,
V_SS = AV_SS = PLLV_SS = 0 V, φ = 32.768 kHz, 2 to 28 MHz*,
T_a = –20°C to +75°C (regular specifications), T_a = –40°C to +85°C (wide-range
specifications)
Item
28MHz
Symbol Min
Max Unit
Test
Conditions
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Clock oscillator settling
time at reset (crystal)
t_cyc
t_CH
t_CL
t_Cr
t_Cf
t_OSC1
35.7 500 ns
10
—
ns
10
—
ns
—
5
ns
—
5
ns
10
—
ms
Figure 26.2
Figure 26.3
Clock oscillator settling time in
software standby (crystal)
t_OSC2
5
—
ms
Figure 24.3
External clock output stabilization
delay time
t_DEXT
2
—
ms
Figure 26.3
32 kHz clock oscillation settling time
t_OSC3
—
2
s
Sub clock oscillator frequency
f_SUB
32.768 32.768 kHz
Sub clock (φ_SUB) cycle time
t_SUB
30.5 30.5 µs
Note: * The input clock frequency should be set to 25 MHz or less. If φ = 25 MHz to 28 MHz, use
the PLL to multiply the frequency (×2 or ×4).
Rev. 5.00 Mar 28, 2005 page 1082 of 1422
REJ09B0234-0500