H8S2633 Datasheet, PDF (1096/1487 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 24 Power-Down Modes
(2) Direct Transitions from Subactive Mode to High-Speed Mode
Execute the SLEEP instruction in subactive mode when the SBYCR SSBY bit = 1, LPWRCR
LSON bit = 0, and DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a direct transition to
high-speed mode after the time set in SBYCR STS2 to STS0 has elapsed.
24.12 φ Clock Output Disabling Function
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 24.6 shows the state of the φ pin in each processing state.
Using the on-chip PLL circuit to lower the oscillator frequency or prohibiting external φ clock
output also have the effect of reducing unwanted electromagnetic interference*. Therefore,
consideration should be given to these options when deciding on system board settings.
Note: * Electromagnetic interference: EMI (Electro Magnetic Interference)
Table 24.6 φ Pin State in Each Processing State
DDR
0
PSTOP
—
Hardware standby mode
High impedance
Software standby mode, watch
mode^*, and direct transition^*
Sleep mode and subsleep mode^*
High impedance
High impedance
High-speed mode, medium-speed High impedance
mode, and subactive mode^*
Note: * This function is not available in the H8S/2695.
1
0
High impedance
Fixed high
φ output
φ output
1
1
High impedance
Fixed high
Fixed high
Fixed high
Rev. 5.00 Mar 28, 2005 page 1034 of 1422
REJ09B0234-0500