H8S2633 Datasheet, PDF (1388/1487 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix C I/O Port Block Diagrams
P1n
*
Internal address bus
Reset
R
Q
D
P1nDDR
C
WDDR1
Reset
R
Q
D
P1nDR
C
WDR1
RDR1
System controller
Address output enable
PPG module
Pulse output enable
Pulse output
TPU module
Output compare output/
PWM output enable
Output compare output/
PWM output
RPOR1
Input capture input
External clock input
Legend:
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
n = 2 or 3
Note: * Priority order: address output > output compare output/PWM output > pulse output > DR output
Figure C.1 (b) Port 1 Block Diagram (Pins P12 and P13)
Rev. 5.00 Mar 28, 2005 page 1326 of 1422
REJ09B0234-0500