H8S2633 Datasheet, PDF (491/1487 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port D Data Register (PDDR)
Bit
:
Initial value :
R/W
:
7
PD7DR
0
R/W
6
PD6DR
0
R/W
5
PD5DR
0
R/W
4
PD4DR
0
R/W
3
PD3DR
0
R/W
2
PD2DR
0
R/W
1
PD1DR
0
R/W
0
PD0DR
0
R/W
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to
PD0).
PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Port D Register (PORTD)
Bit
:7
6
5
4
3
2
1
0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Initial value : —^*
—^*
—^*
—^*
—^*
—^*
—^*
—^*
R/W
:R
R
R
R
R
R
R
R
Note: * Determined by state of pins PD7 to PD0.
PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port D pins (PD7 to PD0) must always be performed on PDDR.
If a PORTD read is performed while PDDDR bits are set to 1, the PDDR values are read. If a
PORTD read is performed while PDDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTD contents are determined by the pin
states, as PDDDR and PDDR are initialized. PORTD retains its prior state by a manual reset or in
software standby mode.
Rev. 5.00 Mar 28, 2005 page 429 of 1422
REJ09B0234-0500