H8S2633 Datasheet, PDF (1455/1487 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix C I/O Port Block Diagrams
Reset
R
Q
D
PA3PCR
C
WPCRA
RPCRA
SCK input
enable
SCK output
SCK output
enable
Reset
R
QD
PA3DDR
C
WDDRA
*1
Reset
PA3
*2
Modes 4 to 6
Address
enable
R
QD
PA3DR
C
WDRA
Reset
R
QD
PA3ODR
C
WODRA
RODRA
RDRA
SCK input
RPORA
Legend:
WDDRA: Write to PADDR
WDRA: Write to PADR
WODRA: Write to PAODR
WPCRA: Write to PAPCR
RDRA: Read PADR
RPORA: Read port A
RODRA: Read PAODR
RPCRA: Read PAPCR
Notes: 1. Output enable signal
2. Open drain control signal
Figure C.18 (d) Port A Block Diagram (Pin PA3)
Rev. 5.00 Mar 28, 2005 page 1393 of 1422
REJ09B0234-0500