H8S2633 Datasheet, PDF (243/1487 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Bit 3
W11
0
1
Bit 2
W10
0
1
0
1
Section 7 Bus Controller
Description
Program wait not inserted when external space area 1 is accessed
1 program wait state inserted when external space area 1 is accessed
2 program wait states inserted when external space area 1 is accessed
3 program wait states inserted when external space area 1 is accessed
(Initial value)
Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of
program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set
to 1.
Bit 1
W01
0
1
Bit 0
W00
0
1
0
1
Description
Program wait not inserted when external space area 0 is accessed
1 program wait state inserted when external space area 0 is accessed
2 program wait states inserted when external space area 0 is accessed
3 program wait states inserted when external space area 0 is accessed
(Initial value)
7.2.4 Bus Control Register H (BCRH)
Bit
:
Initial value :
R/W
:
7
ICIS1
1
R/W
6
ICIS0
1
R/W
5
4
3
2
1
0
BRSTRM BRSTS1 BRSTS0 RMTS2* RMTS1* RMTS0*
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W R/W
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle
insertion, and the memory interface for area 0.
BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Note: * DRAM interface is not available in the H8S/2695.
Only a 0 may be written to RMTS2, RMTS1, or RMTS0.
Rev. 5.00 Mar 28, 2005 page 181 of 1422
REJ09B0234-0500