SH7262 Datasheet, PDF (9/45 Pages) Renesas Technology Corp – High-speed Read/Write Serial Flash Memory

SH7262/SH7264 Group
High-speed Read/Write Serial Flash Memory
Using the Renesas Serial Peripheral Interface
RSPCK
frequency
Set the RSPI as (CPOL=0, CPHA=1)
- Set the RSPCK as 0 when idle
- Latch data on even edge
1
SSL00
RSPCK0
CPOL = 0 setting
changes the RSPCK
polarity.
MOSI0
Master outputs
the last data bit
The timing when the master
latches the first data bit
MISO0
Slave outputs the first data bit
2
Slave outputs the
second data bit
Serial flash memory outputs data on the falling edge,
just after commands are input
The master must latch data on the falling edge of the RSPCK to
ensure one cycle after the timing when the slave outputs data.
-> Use the setting (CPOL=1, CPHA = 0) or (CPOL = 0, CPHA = 1).
Figure 6 Interface Timing on MISO Transfer (CPOL and CPHA bits are changed)
Figure 7 shows the interface timing when extending the setup time. Table 4 and Table 5 list the timing conditions for serial
flash memory and the SH7264. Set the RSPI to satisfy these conditions.
SSL00
t_CSLS
t_LEAD
RSPCK0
MOSI0
MOSI transfer
f_SCK
t_SPcyc
t_DS
t_OD
t_DH
t_OH
MISO0
MISO transfer
t_CSH
t_TD
t_CSLH
t_LAG
t_H
t_V
t_su
t_OH
t_xxx : Timing conditions for serial flash memory
: Timing for latching data
Figure 7 Interface Timing When Extending the Setup Time
REJ06B0889-0100/Rev.1.00
June 2009
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