SH7262 Datasheet, PDF (6/45 Pages) Renesas Technology Corp – High-speed Read/Write Serial Flash Memory

SH7262/SH7264 Group
High-speed Read/Write Serial Flash Memory
Using the Renesas Serial Peripheral Interface
2.3.2 Extending the Setup Time and the Access Width
This section describes RSPI setting and the interface timing when accessing serial flash memory in high-speed.
This example extends the setup time to one cycle, to specify the RSPCK as 36 MHz, and extends the access width to the
data register (SPDR) on data transfer to the longword-wide (32-bit). As this procedure requires a complex control, however,
it allows the SPI to transfer data efficiently.
(1) Extending the Setup Time
The setup time by the typical control procedure described in 2.3.1 is less than half a cycle of the RSPCK. The SH7264 data
input setup time (t_SU) is 15 ns at minimum. When setting the RSPCK frequency at 36 MHz at maximum (when the bus
clock is 72 MHz), the half cycle is approximately 13 ns at minimum. As it does not satisfy the timing condition, extend the
setup time to allow the RSPCK frequency at 36 MHz.
Following example describes how to extend the setup time when using the Read Array command.
The figure below shows the command sequence for the Read Array command (Opcode: H'0B). The former part of the
transfer is MOSI, the SH7264 (Master) outputs commands and addresses. The latter part of the transfer is MISO, the serial
flash memory (Master) outputs data. To extend the setup time, change CPOL and CPHA bits settings in the SPCMD register
in the former part and latter part of the transfer. Table 3 describes the CPOL bit and the CPHA bit.
MOSI transfer (Refer to Figure 4)
MISO transfer (Refer to Figures 5 and 6)
SSL00
MOSI0
H'0B addr1 addr2 addr3 dummy
MISO0
data1 data2 data2
data n-1 data n
Figure 3 Command Sequence When Extending the Setup Time (Read Array Command)
Table 3 CPOL Bit and CPHA bit
Register Name Bit Bit Name R/W Description
Command
1 CPOL
register (SPCMD)
R/W RSPCK Polarity Setting
Specifies the RSPCK polarity in master or slave mode. When
transferring/receiving data between the RSPI and the other module,
set the polarity of the RSPCK at the same level.
0: RSPCK = 0 when idle
1: RSPCK = 1 when idle
0 CPHA
R/W RSPCK Phase Setting
Specifies the RSPCK phase in master or slave mode. When
transferring/receiving data between the RSPI and the other module,
set the phase of the RSPCK at the same level.
0: Latches the data on odd edge, and outputs data on even edge
1: Outputs data on odd edge, and latches on even edge
REJ06B0889-0100/Rev.1.00
June 2009
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