SH7262 Datasheet, PDF (14/45 Pages) Renesas Technology Corp – High-speed Read/Write Serial Flash Memory

SH7262/SH7264 Group
High-speed Read/Write Serial Flash Memory
Using the Renesas Serial Peripheral Interface
2.4.2 Command Transfer Example
The sample program supports two types of command, the Read command that uses both the master output and slave output,
and the Write command that uses the master output only. Figure 11 to Figure 13 show the flow charts of the read command
transfer. The access width when reading data is specified in longword (32-bit). Use the DMA transfer to store data in
memory.
Figure 14 shows the flow chart of the write command transfer. As the busy time is longer than the time to transfer
commands, the access width is specified in byte-wide in this example.
Read command transfer
Reset the transmit/receive buffers
Enable the SPI to transfer data
Extend the setup time for MOSI
direction (Master to Slave)
Transferred
Yes
all commands?
No
Write command in the Data register
• Set the SPBFCR register (SPBFCR = 0xC0, SPBFCR = 0x00)
Function: Reset the data in the transmit/receive buffers
(It should be cleared to 0 every time the data is written.)
• Set the SPCR register (SPE bit = 1)
Function: Enable the RSPI
(This register enables the RSPI transfer function.)
• Set the SPCMD register (CPOL bit = 1, CPHA bit = 0)
Functions:
(1) Specify the RSPCK when idling as 1
(2) Specify the RSPCK to output data on even edge
• Transfer data (opcode and address bytes for the command sequence) output
by the master. Five bytes in total (opcode 0x0B, three bytes address, and
dummy byte) are transferred when the Read Array is issued.
• Command size must be equal or less than eight bytes to avoid the transmit
FIFO overflow.
Wait for the transfer end
Extend the setup time for MISO
direction (Slave to Master)
Reset the transmit/receive buffers
Extend the access width to longword
B
• Set the SPCMD register (CPOL bit = 0, CPHA bit = 1)
Functions:
(1) Specify the RSPCK when idling as 0
(2) Latch data on odd edge
• Set the SPDCR register (SPLW bit = 3)
Function: Specify the access width to the SPDR register as 32-bit
• Set the SPCMD register (SPB bit = 3)
Function: Specify the transfer data length as 32-bit
Figure 11 Flow Chart of the Read Command Transfer (1/3)
REJ06B0889-0100/Rev.1.00
June 2009
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