SH7262 Datasheet, PDF (5/45 Pages) Renesas Technology Corp – High-speed Read/Write Serial Flash Memory

SH7262/SH7264 Group
High-speed Read/Write Serial Flash Memory
Using the Renesas Serial Peripheral Interface
2.3 Interface Timing Example When Accessing in High-speed
This section describes an example of the interface timing when accessing serial flash memory in high-speed. The interface
timing by the typical procedure to control the SPI is explained, as well as the procedure to read/write serial flash memory in
high-speed.
2.3.1 Interface Timing by the Typical Procedure to Control SPI
Figure 2 shows an example of the data transfer timing by the typical procedure to control SPI. According to the
specifications of the serial flash memory used in this application, both master and slave output data on the falling edge of
the clock, and latch data on the rising edge of the clock after a half cycle later. This procedure supports full-duplex
communication.
For details on this procedure, refer to the application note "SH7262/SH7264 Group Interfacing Serial Flash Memory Using
the Renesas Serial Peripheral Interface".
SSL00
t_CSLS
t_LEAD
RSPCK0
fSCK
t_SPcyc
tOD
t_OH
t_DS
t_DH
t_CSH
t_TD
t_CSLH
t_LAG
MOSI0
bit 0
bit 1
t_V
t_su
t_OH
tH
bit 7
MISO0
t_xxx : Timing conditions for serial flash memory
: Timing for latching data
Figure 2 Data Transfer Timing Example by the Typical Procedure to Control SPI (CPOL = 1, CPHA =1)
REJ06B0889-0100/Rev.1.00
June 2009
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