SH7262 Datasheet, PDF (8/45 Pages) Renesas Technology Corp – High-speed Read/Write Serial Flash Memory

SH7262/SH7264 Group
High-speed Read/Write Serial Flash Memory
Using the Renesas Serial Peripheral Interface
This section describes the MISO transfer.
As the master latches data in the MISO transfer, set CPOL and CPHA bits so that the master latches data one cycle after the
slave outputs data. As the serial flash memory used in this application outputs data on the falling edge, the SH7264 must
latches data on the preceding edge (falling edge). (CPOL =1, CPHA = 0) setting is already used in the MOSI transfer,
however, change the setting to (CPOL 0, CPHA = 1) for the following reason.
Figure 5 shows the timing without changing the settings of CPOL and CPHA bits. As the master latches data when the slave
outputs data on the falling edge of the RSPCK falling edge, this setting does not satisfy the timing condition.
Figure 6 shows the timing for (CPOL = 0, CPHA = 1). As the RSPCK falls when changing the RSPI setting, the slave
outputs data at the same timing. Then, the master latches data one cycle after the falling edge of the RSPCK. This setting
satisfies the timing condition.
RSPCK
frequency
SSL00
1
2
Serial flash memory outputs data on falling edge, just
after commands are input.
RSPCK0
MOSI0
Master outputs
the last data bit
MISO0
Slave outputs the
first data bit
The timing when the master
latches the first data bit
Slave outputs the
second data bit
Figure 5 Interface Timing on MISO Transfer (CPOL and CPHA bits are not changed)
REJ06B0889-0100/Rev.1.00
June 2009
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