SH7262 Datasheet, PDF (32/45 Pages) Renesas Technology Corp – High-speed Read/Write Serial Flash Memory

SH7262/SH7264 Group
High-speed Read/Write Serial Flash Memory
Using the Renesas Serial Peripheral Interface
3.14 Sample Program Listing "serial_flash.c" (11/19)
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/* ==== RSPI ==== */
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RSPI0.SPCR.BYTE = 0x00; /* Disables channel 0 of the RSPI */
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RSPI0.SPPCR.BYTE = 0x30; /* MOSI idle fixed value = 1 */
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RSPI0.SPBR.BYTE = 0x00; /* Specifies the base bit rate as 36 MHz
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(Bus clock = 72 MHz) */
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RSPI0.SPDCR.BYTE = 0x20; /* Disables to transmit the dummy data */
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/* Access width to the SPDR register: 8-bit */
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RSPI0.SPCKD.BYTE = 0x00; /* RSPCK delay: 1 RSPCK */
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RSPI0.SSLND.BYTE = 0x00; /* SSL negate delay: 1 RSPCK */
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RSPI0.SPND.BYTE = 0x00; /* Next access delay: 1 RSPCK + 2 Bus clocks */
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RSPI0.SPSCR.BYTE = 0x00; /* Sequence length: 1 (SPCMD0 is only used) */
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RSPI0.SPCMD0.WORD = 0xE780; /* MSB first */
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/* Data length: 8-bit */
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/* Keeps the SSL signal level after transfer
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is completed */
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/* Bit rate: Base bit rate is not divided */
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/* RSPCK when idling is 0 */
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/* Latches data on odd edge, outputs data on even edge */
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RSPI0.SPBFCR.BYTE = 0xC0; /* Enables to reset data in the
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transmit/receive buffer */
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RSPI0.SPBFCR.BYTE = 0x00; /* Disables to reset data in the
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transmit/receive buffer */
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/* Number of triggers in transmit buffer:
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more than one byte available */
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/* Number of triggers in receive buffer:
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more than one byte received */
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RSPI0.SSLP.BYTE = 0x00; /* SSLP = b'0 SSL signal 0-active */
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RSPI0.SPCR.BYTE = 0x48; /* Master mode */
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/* Disables interrupts */
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/* Enables channel 0 of the RSPI */
470 }
REJ06B0889-0100/Rev.1.00
June 2009
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