SH7262 Datasheet, PDF (17/45 Pages) Renesas Technology Corp – High-speed Read/Write Serial Flash Memory

Write command transfer
Reset the transmit/receive buffers
Enable the SPI to transfer data
Extend the setup time for MOSI
direction (Master to Slave)
Transferred
Yes
all commands?
No
Write command in the Data register
SH7262/SH7264 Group
High-speed Read/Write Serial Flash Memory
Using the Renesas Serial Peripheral Interface
• Set the SPBFCR register (SPBFCR = H'C0, SPBFCR = H'00)
Function: Reset the data in the transmit/receive buffer
(It should be cleared to 0 every time the data is written)
• Set the SPCR register (SPE bit = 1)
Function: Enable the RSPI
This register enables the RSPI transfer function. As there is a
register not allowing to rewrite data when SP bit is 1, pay close
attention when setting this register. The Command register
(SPCMD) does not restrict the the SPE bit value when the TEND
bit is 1.
• Set the SPCMD register (CPOL bit = 1, CPHA bit = 0)
Functions:
(1) Specify the RSPCK when idling as 1
(2) Output data on even edge
• Transfer data (opcode and address bytes for command sequence) output
by the master
• Command size must be equal or less than eight bytes to avoid the transmit
FIFO overflow.
Transferred all data
Yes
to write?
No
No
Transmit FIFO
is empty?
Yes
Write data in the Data register
No
Any data exists in
the receive FIFO?
Yes
Read the Data register
• Read the dummy data as the RSPI transfer stops when the receive FIFO
overflows upon the RSPI is operating as the master.
Wait for the transfer end
Disable the SPI to transfer data
End
• Set the SPCR register (SPE bit = 0)
Function: Disable the RSPI
This register disables the RSPI transfer function. The SSL signal is
negated by this setting.
Figure 14 Flow Chart of the Write Command Transfer
REJ06B0889-0100/Rev.1.00
June 2009
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