RX62N Datasheet, PDF (9/25 Pages) Renesas Technology Corp – 100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash, Ethernet, USB 2.0

RX62N Group and RX621 Group
16-Bit SDRAM Connection and Access Examples
4.4 SDRAM Timing Settings
In this application note, the access timings are set to match the specifications of the SDRAM used. It is necessary to
observe the access timings stipulated in the SDRAM data sheet when accessing SDRAM. The methods for determining
the setting values are shown below. Table 6 lists the setting values used.
(1) SDRAMC column latency setting
Since the SDRAM used in this application note can be operated with a CAS latency of from 1 to 3 cycles, in this
application note, the CAS latency is set to 3 cycles.
Therefore the SDRAMC column latency setting bits (CL[2:0]) are set to 011b.
(2) Write recovery period setting
Since the SDRAM used in this application note has a write recovery period (tWR) of 28.3 ns (minimum), the
SDRAMC write recovery period is set to meet the following condition
28.3 ns (min) ≤ write recovery period
Since
28.3 ns/(1/48 MHz) = 1.36 cycles,
A write recovery period of at least 2 cycles is required.
Therefore the write recovery period setting bit (WR) is set to 1b.
(3) Row precharge period setting
Since the SDRAM used in this application note has a row precharge period (tRP) of 20 ns (minimum), the
SDRAMC row precharge period must meet the following condition.
20 ns (min) ≤ row precharge period
Since
20 ns/(1/48 MHz) = 0.96 cycles,
a row precharge period of at least 1 cycle is required.
Therefore the row precharge period setting bits (RP[2:0]) are set to 000b.
(4) Row active period setting
Since the SDRAM used in this application note has a period (tRAS) from an active command to a precharge
command of 44 ns (minimum), the SDRAMC row active period will be:
44 ns (min) ≤ row active period
Since
44 ns/(1/48 MHz) = 2.11 cycles,
a row active period of at least 3 cycles is required.
Therefore the row active period setting bits (RAS[2:0]) are set to 010b.
Note that the SDRAMC row active period setting bits must be set so that the following stipulation is observed.
Row active period ≤ row column latency + SDRAC column latency
R01AN0585EJ0202 Rev.2.02
Feb 14, 2014
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