RX62N Datasheet, PDF (16/25 Pages) Renesas Technology Corp – 100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash, Ethernet, USB 2.0

RX62N Group and RX621 Group
16-Bit SDRAM Connection and Access Examples
SDRAM refresh control register (SDRFCR) Bits: 16, Address: 0008 3C14h
Bit
Symbol Setting Name
Function
R/W
b11-b0 RFC[11:0 2EDh Auto refresh required interval 001011101101: 749 cycles
R/W
]
setting bits
b15-b12 REFW 0011 Auto refresh cycle/auto
0011: 4 cycles
R/W
[3:0]
refresh release cycle setting
bits
SDRAM auto refresh control register (SDRFEN) Bits: 8, Address: 0008 3C16h
Bit
Symbol Setting Name
Function
R/W
b0
RFEN
1
Auto refresh operation enable 1: Auto refresh operation enable
R/W
bit
SDC mode register (SDCMOD) Bits: 8, Address: 0008 3C01h
Bit
Symbol Setting Name
b0
EMODE 0
Endian specification bit
Function
R/W
0: The SDRAM address space
R/W
endian operation is set to be the
same as the operating mode
endian setting.
SDRAM access mode register (SDAMOD) Bits: 8, Address: 0008 3C02h
Bit
Symbol Setting Name
Function
R/W
b0
BE
0
Continuous access enable 0: Continuous access disabled
R/W
SDRAM address register (SDADR) Bits: 8, Address: 0008 3C40h
Bit
Symbol Setting Name
Function
R/W
b1-b0 MXC[1:0] 01
Address multiplexing
01: 9-bit shift
R/W
selection bit
SDRAM timing register (SDTR) Bits: 32, Address: 0008 3C44h
Bit
Symbol Setting Name
Function
R/W
b2-b0 CL[2:0] 011
SDRAMC column latency
011: 3 cycles
R/W
setting bits
b8
WR
1
Write recovery period setting 1: 2 cycles
R/W
bit
b11-b9 RP[2:0] 000
Row precharge period setting 000: 1 cycle
R/W
bits
b13-b12 RCD[1:0] 00
Row column latency setting 00: 1 cycle
R/W
bits
b18-b16 RAS[2:0] 010
Row active period setting bits 010: 3 cycles
R/W
R01AN0585EJ0202 Rev.2.02
Feb 14, 2014
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