RX62N Datasheet, PDF (4/25 Pages) Renesas Technology Corp – 100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash, Ethernet, USB 2.0

RX62N Group and RX621 Group
16-Bit SDRAM Connection and Access Examples
4. Operating Description
4.1 SDRAM Initialization Sequence Setup
Before accessing the SDRAM used, it is necessary to initialize that SDRAM. This initialization should be performed
once after a reset. The initialization sequence must observe the initialization auto refresh interval, initialization auto
refresh count, and initialization precharge cycle stipulated in the SDRAM's data sheet. The methods for determining the
setting values are shown below. Table 3 lists the setting values.
(1) Initialization auto refresh interval
Since the auto refresh interval (tRFC) for the SDRAM used in this application note is 66 ns (minimum), the
SDRAMC initialization auto refresh interval must meet the following condition.
66 ns (min) ≤ initialization auto refresh interval
Also, since the SDRAM clock (SDCLK) setting used in this application note is 48 MHz, the SDCLK period will be
1/48 MHz.
Therefore,
66 ns (min)/(1/48 MHz) = 3.17 cycles
Accordingly, an initialization auto refresh period of at least 4 cycles is required.
Therefore the initialization auto refresh period bits (ARFI[3:0]) are set to 0001b.
(2) Initialization auto refresh count
The SDRAM used in this application note requires that the initialization auto refresh operation be performed twice.
Therefore the initialization auto refresh count bits (ARFC[3:0]) are set to 0010b.
(3) Initialization precharge cycle
Since the precharge command period (tRP) for the SDRAM used in this application note is 20 ns (minimum), the
SDRAMC initialization precharge cycle count must meet the following condition.
20 ns (min) ≤ initialization precharge cycle count
Since
20 ns/(1/48 MHz) = 0.96 cycles,
at least one SDRAM initialization precharge cycle is required. However, since fewer than 3 cycles cannot be set
according to the RX62N SDRAMC specifications, the set value will be 3 cycles.
Therefore the initialization precharge cycle count setting bits (PRC[2:0]) are set to 000b.
R01AN0585EJ0202 Rev.2.02
Feb 14, 2014
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