RX62N Datasheet, PDF (10/25 Pages) Renesas Technology Corp – 100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash, Ethernet, USB 2.0

RX62N Group and RX621 Group
16-Bit SDRAM Connection and Access Examples
(5) Row column latency setting
Since the SDRAM used in this application note has a delay time (tRCD) of 20 ns (minimum) from the point an
active command is issued until a read/write command is issued, the SDRAMC row column latency will be:
20 ns (min) ≤ row column latency
Since
20 ns/(1/48 MHz) = 0.96 cycles,
A row column latency of at least 1 cycle must be set.
To observe stipulations on the SDRAMC row active period setting bits, the following condition must be observed.
Row active period ≤ row column latency + SDRAMC column latency
In this application note, the row active period is set to 3 cycles and the SDRAMC column latency is also set to 3
cycles. Here, we determined the row column latency setting cycles using the above formula.
Row column latency setting cycle count ≥ (3 cycles) – (3 cycles)
≥ 0 cycles
However, since the row column latency setting bits (RCD[1:0]) cannot be set to 0 cycles, in this application note,
this field is set to 1 cycle, or 00b.
Table 6 SDRAM Timing Register (SDTR)
Bit Name
SDRAMC column latency setting bits (CL[2:0])
Write recovery period setting bit (WR)
Row precharge period setting bits (RP[2:0])
Row active period setting bits (RAS[2:0])
Row column latency setting bits (RCD[1:0])
Setting Value
011b
1b
000b
010b
00b
Function
3 cycles
2 cycles
1 cycle
3 cycles
1 cycle
Single read
SDCLK
SDRAM command ^{ACT RD} DSL PRA
Data bus
d0
RCD: 1 cycle CL: 3 cycles
RP: 1 cycle
RAS: 3 cycles
ACT: Bank active command
RD: Read command
PRA: All banks precharge command
DSL: Device deselect command
Figure 5 Read Timing
R01AN0585EJ0202 Rev.2.02
Feb 14, 2014
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