RX62N Datasheet, PDF (6/25 Pages) Renesas Technology Corp – 100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash, Ethernet, USB 2.0

RX62N Group and RX621 Group
16-Bit SDRAM Connection and Access Examples
4.2 SDRAM Mode Register Settings
After SDRAM initialization, the SDRAM mode register must be set. The mode must be set once and only once after
initialization. With the RX62N SDRAMC, the SDRAM mode register can be written automatically by setting the
SDRAM mode register (SMOD). Table 4 lists the setting values.
(1) Mode register
The RX62N SDRAMC operates with a burst length of 1. Operation is not guaranteed if a burst length other then 1 is
set. This application note uses a burst length of 1, a column latency of 3 cycles, and single access mode.
Table 4 SDRAM Mode Register (SDMOD)
Bit Name
Mode register setting bits (MR[14:0])
Setting Value
230h
Function
A burst length of 1,
a column latency of 3 cycles,
and single access mode.
SDCLK
Mode register
setting cycle
SDRAM command MRS DSL DSL
Address bus
A
3 cycles (Fixed)
DSL: Device deselect
MRS: Mode register setting command
Figure 3 SDRAM Mode Register Setting Timing
R01AN0585EJ0202 Rev.2.02
Feb 14, 2014
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