R10DS0216EJ0100 Datasheet, PDF (9/14 Pages) Renesas Technology Corp – 4Mb Advanced LPSRAM

RMLV0414E Series
Write Cycle (2) (WE# CLOCK, OE# Low Fixed)
A_0~17
t_WC
Valid address
t_CW
CS#
LB#,UB#
WE#
t_AW
t_AS
t_BW
t_WP ^*20
t_WR
OE#
OE# = “L” level VIL
I/O_0~15
t_WHZ ^*21,22
t_OW
*23
Valid Data
*23
t_DW
t_DH
Note
20. t_WP is the interval between write start and write end.
A write starts when all of (CS#), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS#, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS#), (WE#) or (one or both of LB# and UB#) becomes inactive.
21. t_WHZ is defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O
levels.
22. This parameter is sampled and not 100% tested.
23. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins.
R10DS0216EJ0100 Rev.1.00
2014.2.27
Page 9 of 12