R10DS0216EJ0100 Datasheet, PDF (11/14 Pages) Renesas Technology Corp – 4Mb Advanced LPSRAM

RMLV0414E Series
Write Cycle (4) (LB#,UB# CLOCK)
A_0~17
CS#
t_WC
Valid address
t_AW
t_CW
LB#,UB#
t_AS
t_BW
t_WR
WE#
t_WP ^*25
OE#
V_IH
OE# = “H” level
I/O_0~15
t_DW
t_DH
Valid Data
Note
25. t_WP is the interval between write start and write end.
A write starts when all of (CS#), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS#, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS#), (WE#) or (one or both of LB# and UB#) becomes inactive.
R10DS0216EJ0100 Rev.1.00
2014.2.27
Page 11 of 12