R10DS0216EJ0100 Datasheet, PDF (8/14 Pages) Renesas Technology Corp – 4Mb Advanced LPSRAM

RMLV0414E Series
Write Cycle (1) (WE# CLOCK, OE#=”H” while writing)
A_0~17
t_WC
Valid address
t_CW
CS#
LB#,UB#
WE#
OE#
I/O_0~15
t_BW
t_AW
t_AS
t_WP ^*16
t_WR
t_WHZ ^*17,18
t_OHZ ^*17,18
*19
t_DW
t_DH
Valid Data
Note
16. t_WP is the interval between write start and write end.
A write starts when all of (CS#), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS#, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS#), (WE#) or (one or both of LB# and UB#) becomes inactive.
17. t_OHZ and t_WHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to
the I/O levels.
18. This parameter is sampled and not 100% tested.
19. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins.
R10DS0216EJ0100 Rev.1.00
2014.2.27
Page 8 of 12