R10DS0216EJ0100 Datasheet, PDF (12/14 Pages) Renesas Technology Corp – 4Mb Advanced LPSRAM

RMLV0414E Series
Low V_CC Data Retention Characteristics
Parameter
V_CC for data retention
Data retention current
Symbol Min. Typ. Max. Unit
Test conditions^*27
Vin ≥ 0V,
V_DR
1.5
─
─
V ^{(1) CS# ≥ VCC-0.2V or}
(2) LB# = UB# ≥ V_CC-0.2V,
CS# ≤ 0.2V
I_CCDR
─
0.4^*26
2
─
─
3
─
─
5
─
─
7
A ~+25°C
A
~+40°C
V_CC=3.0V, Vin ≥ 0V,
(1) CS# ≥ V_CC-0.2V or
A ~+70°C ^{(2) LB# = UB# ≥ VCC-0.2V,}
CS# ≤ 0.2V
A ~+85°C
Chip deselect time to data retention
t_CDR
Operation recovery time
t_R
0
5
─
─
─
─
ns
ms
See retention waveform.
Note 26. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
27. CS# controls address buffer, WE# buffer, OE# buffer, LB# buffer, UB# buffer and I/O buffer. If CS# controls
data retention mode, Vin levels (address, WE#, OE#, LB#,UB#, I/O) can be in the high-impedance state.
Low Vcc Data Retention Timing Waveforms (CS# controlled)
CS# Controlled
V_CC
2.2V
t_CDR
CS#
2.7V 2.7V
t_R
V_DR
CS# ≥ V_CC - 0.2V
2.2V
Low Vcc Data Retention Timing Waveforms (LB#,UB# controlled)
LB#,UB# Controlled
V_CC
t_CDR
2.2V
LB#,UB#
2.7V 2.7V
t_R
V_DR
LB#,UB# ≥ V_CC - 0.2V
2.2V
R10DS0216EJ0100 Rev.1.00
2014.2.27
Page 12 of 12