HD151BF854 Datasheet, PDF(9/13 Page) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Application

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HD151BF854 Datasheet, PDF (9/13 Pages) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Application

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HD151BF854

Electrical Characteristics

Item

Symbol Min

Typ *1 Max Unit Test Conditions

Input clamp voltage

(All inputs)

VIK

â1.2 V

II = â18 mA, VDD = 2.3 V

Output voltage

VOH

VDDâ0.2 â

IOH = â100 ÂµA, VDD = 2.3 to 2.7

Input current

1.7

VDD

IOH = â12 mA, VDD = 2.3 V

VOL

0.2

IOL = 100 ÂµA, VDD = 2.3 to 2.7 V

0.6

IOL = 12 mA, VDD = 2.3 V

â10

ÂµA VI = 0 V or 2.7 V,

VDD = 2.7 V, CLKIN, FBIN

Analog supply current

AICC

mA VDD = AVDD = 2.7 V,

170 MHz

Dynamic supply current DICC

250 300 mA VDD = AVDD = 2.7 V,

170 MHz

All Yn, Yn, = open

Input capacitance*2

Delta input capacitance*2 CDi

2.5

â0.25 â

3.5

pF CLKIN and FBIN

0.25 pF

Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended

operating conditions.

2. Target of design, not 100% tested in production.

Rev.4, Jan. 2003, page 7 of 11

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