HD151BF854 Datasheet, PDF (10/13 Pages) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Application

HD151BF854
Switching Characteristics
Ta = 25°C, VDD = AVDD = 2.5V
Item
Symbol Min
Typ
Max
Unit Test Conditions & Notes
Period jitter
Half period jitter
t_PER
—
t_HPER
—
|75|
—
|120| —
ps *^{7, 8}
ps *⁸
Cycle to cycle jitter
Static phase offset
t_CC
—
t_sPE
—
|75|
—
|150| —
ps
ps *^{4, 5}
Output clock skew
t_sk
—
Operating clock frequency f_CLK(O) 60
Application clock
frequency
f_CLK(A)
80
150
—
ps
—
210
MHz *^{1, 2}
166
210
MHz *^{1, 3}
Slew rate
Stabilization time
1.0
—
—
—
2.0
V/ns 20% to 80%
0.1
ms *⁶
Notes: Target of design, not 100% tested in production.
1. The PLL must be able to handle spread spectrum induced skew. (the specification for this
frequency modulation can be found in the latest Intel PC100 Registered DIMM specification)
2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in
which it is not required to meet the other timing parameters. (Used for low speed system debug.)
3. Application clock frequency indicates a range over which the PLL must meet all timing
parameters.
4. Assumes equal wire length and loading on the clock output and feedback path.
5. Static phase offset does not include jitter.
6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of it’s
feedback signal to it’s reference signal after power on.
7. Period jitter defines the largest variation in clock period, around a nominal clock period.
8. Period jitter and half period jitter are separate specifications that must be met independently of
each other.
Rev.4, Jan. 2003, page 8 of 11