HD151BF854 Datasheet, PDF (5/13 Pages) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Application

Pin Arrangement
HD151BF854
Y0 1
Y0 2
VDD 3
Y1 4
Y1 5
GND 6
NC 7
CLKIN 8
NC 9
AVDD 10
AGND 11
VDD 12
Y2 13
Y2 14
28 GND
27 Y5
26 Y5
25 Y4
24 Y4
23 VDD
22 NC
21 NC
20 FBIN
19 FBOUT
18 NC
17 Y3
16 Y3
15 GND
(Top view)
Rev.4, Jan. 2003, page 3 of 11