HD151BF854 Datasheet, PDF(11/13 Page) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Application

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HD151BF854 Datasheet, PDF (11/13 Pages) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Application

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HD151BF854

Zo = 60 â¦

RT=

C = 14 pF

120 â¦

Zo = 60 â¦

C = 14 pF

Note: 1. SDRAM Cin 3.5 pF Ã4

Figure 1 Clock outputs test circuit

tcycle n

tcycle n+1

t CC = (tcycle n) - (tcycle n+1)

Figure 2 Cycle to cycle jitter

tsk

Figure 3 Output clock skew (Differential clock output)

Rev.4, Jan. 2003, page 9 of 11

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