HD151BF854 Datasheet, PDF (3/13 Pages) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Application

HD151BF854
2.5 V PLL Clock Buffer for DDR Application
ADE-205-696D (Z)
Preliminary
Rev.4
Jan. 2003
Description
The HD151BF854 is a high-performance, low-skew, low-jitter, PLL clock buffer. It is specifically
designed for use with DDR (Double Data Rate) PC mother board application.
Features
• Designed for DDR200/266/333/400 PC mother board clock buffering
• Supports 60 MHz to 210 MHz operation range
• Distributes one to six differential clock outputs pairs
• Spread spectrum clock compatible
• External feedback pin (FBIN) is used to synchronize the outputs to the clock input
• Supports 2.5 V analog supply voltage (AVDD), and 2.5 V VDD
• Ordering Information
Part Name
Package Type
Package Code Package
Abbreviation
HD151BF854SSEL SSOP-28 pin
SSOP-28
SS
Note: Please consult the sales office for the above package availability.
Taping
Abbreviation (Quantity)
EL (1,000 pcs / Reel)