HD151BF854 Datasheet, PDF(7/13 Page) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Application

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HD151BF854 Datasheet, PDF (7/13 Pages) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Application

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Logic Diagram

AVDD 10

Test

Logic

CLKIN 8

PLL

FBIN 20

HD151BF854

2 Y0

4 Y1

5 Y1

13 Y2

17 Y3

24 Y4

26 Y5

19 FBOUT

Note: All inputs and outputs are associated with VDDQ = 2.5 V.

Rev.4, Jan. 2003, page 5 of 11

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