HD151BF854 Datasheet, PDF (4/13 Pages) Renesas Technology Corp – 2.5 V PLL Clock Buffer for DDR Application

HD151BF854
Key Specifications
• Supply voltages: VDD = AVDD = 2.5 V±0.2 V
• Output clock cycle to cycle jitter = ±75 ps
• Output clock pin to pin skew = 150 ps
Function Table
Inputs
AVDD
GND
GND
2.5 V (typ.)
2.5 V (typ.)
H: High level
L: Low level
CLK
L
H
L
H
Outputs
Yn
Yn
L
H
H
L
L
H
H
L
FBOUT
L
H
L
H
PLL
Bypass / Off
Bypass / Off
Running
Running
Rev.4, Jan. 2003, page 2 of 11