H8S43 Datasheet, PDF (834/1279 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 18 I²C Bus Interface [Option]
Slave transmit mode
Clear IRIC in ICCR
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1?
[1] Set transmit data for the second and
subsequent bytes.
[1]
[2] Wait for 1 byte to be transmitted.
[3] Test for end of transfer.
[4] Select slave receive mode.
[5] Dummy read (to release the SCL line).
[2]
Yes
Read ACKB in ICSR
[3]
End
No
of transmission
(ACKB = 1)?
Yes
Set TRS = 0 in ICCR
[4]
Read ICDR
[5]
Clear IRIC in ICCR
End
Figure 18.17 Flowchart for Slave Receive Mode (Example)
18.3.10 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2)
clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 18.2.8, DDC
Switch Register (DDCSWR).
Rev. 3.00 Jan 11, 2005 page 778 of 1220
REJ09B0186-0300O