H8S43 Datasheet, PDF (518/1279 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 11 16-Bit Timer Pulse Unit (TPU)
11.2.4 Timer Interrupt Enable Register (TIER)
Channel 0: TIER0
Channel 3: TIER3
Bit
:7
6
TTGE
—
Initial value : 0
1
R/W
: R/W
—
5
4
3
2
1
0
—
TCIEV TGIED TGIEC TGIEB TGIEA
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
Channel 1: TIER1
Channel 2: TIER2
Channel 4: TIER4
Channel 5: TIER5
Bit
:7
6
5
4
3
TTGE
—
TCIEU TCIEV
—
Initial value : 0
1
0
0
0
R/W
: R/W
—
R/W
R/W
—
2
1
0
—
TGIEB TGIEA
0
0
0
—
R/W
R/W
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has six TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset, and in hardware standby mode.
Rev. 3.00 Jan 11, 2005 page 462 of 1220
REJ09B0186-0300O