H8S43 Datasheet, PDF (583/1279 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 11 16-Bit Timer Pulse Unit (TPU)
(10) Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 11.56 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
φ
TCNT input
clock
TCNT
H'FFFF
H'0000
Counter
clear signal
TGF
TCFV
Prohibited
Figure 11.56 Contention between Overflow and Counter Clearing
Rev. 3.00 Jan 11, 2005 page 527 of 1220
REJ09B0186-0300O