H8S43 Datasheet, PDF (211/1279 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 7 Bus Controller
Bits 2 to 0—Refresh Counter Clock Select (CKS2 to CKS0): These bits select from the seven
internal clocks derived by dividing the system clock (φ) to be input to RTCNT. The RTCNT count
up starts when CKS2 to CKS0 are set to select the input clock.
Bit 2
CKS2
0
1
Bit 1
CKS1
0
1
0
1
Bit 0
CKS0
0
1
0
1
0
1
0
1
Description
Stops count
Counts on φ/2
Counts on φ/8
Counts on φ/32
Counts on φ/128
Counts on φ/512
Counts on φ/2048
Counts on φ/4096
(Initial value)
7.2.9 Refresh Timer Counter (RTCNT)
Bit
:
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RTCNT is an 8-bit read/write up-counter.
RTCNT counts up using the internal clock selected by the DRAMCR CKS2 to CKS0 bits.
When RTCNT matches the value in RTCOR (compare match), the DRAMCR CMF flag is set to 1
and RTCNT is cleared to H'00. If, at this point, DRAMCR RFSHE is set to 1, the refresh cycle
starts. When the DRAMCR CMIE bit is set to 1, a compare match interrupt (CMI) is also
generated.
RTCNT is initialized to H'00 at a power-on reset and in hardware standby mode. It is not
initialized at a manual reset or in software standby mode.
Rev. 3.00 Jan 11, 2005 page 155 of 1220
REJ09B0186-0300O