H8S43 Datasheet, PDF (795/1279 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 18 I²C Bus Interface [Option]
18.2.2 Slave Address Register (SAR)
Bit
:7
6
5
4
3
2
1
0
SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS
Initial value : 0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SAR is an 8-bit readable/writable register that stores the slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SAR is assigned to the same
address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SAR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 1—Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0,
differing from the addresses of other slave devices connected to the I²C bus.
Bit 0—Format Select (FS): Used together with the FSX bit in SARX to select the communication
format.
• I²C bus format: addressing format with acknowledge bit
• Synchronous serial format: non-addressing format without acknowledge bit, for master mode
only
The FS bit also specifies whether or not SAR slave address recognition is performed in slave
mode.
Rev. 3.00 Jan 11, 2005 page 739 of 1220
REJ09B0186-0300O