H8S43 Datasheet, PDF (159/1279 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 5 Interrupt Controller
• The interrupt priority level can be set by means of IPR.
• The DMAC and DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request.
When the DMAC and DTC are activated by an interrupt, the interrupt control mode and
interrupt mask bits are not affected.
5.3.3 Interrupt Exception Handling Vector Table
Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority.
Priorities among modules can be set by means of the IPR. The situation when two or more
modules are set to the same priority, and priorities within a module, are fixed as shown in table
5.4.
Rev. 3.00 Jan 11, 2005 page 103 of 1220
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