H8S43 Datasheet, PDF (662/1279 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Watchdog Timer
15.2.3 Reset Control/Status Register (RSTCSR)
Bit
:7
6
5
4
3
2
1
0
WOVF RSTE RSTS
—
—
—
—
—
Initial value : 0
0
0
1
1
1
1
1
R/W
: R/(W)* R/W
R/W
—
—
—
—
—
Note: * Only 0 can be written, for flag clearing.
RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RES RSTCSR is initialized to H'1F by a reset signal from the pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
see section 15.2.5, Notes on Register Access.
Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from
H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.
Bit 7
WOVF
0
1
Description
[Clearing condition]
(Initial value)
• Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF
[Setting condition]
• Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the
H8S/2643 Group if TCNT overflows during watchdog timer operation.
Bit 6
RSTE
Description
0
Reset signal is not generated if TCNT overflows*
(Initial value)
1
Reset signal is generated if TCNT overflows
Note: * The modules within the H8S/2643 Group are not reset, but TCNT and TCSR within the
WDT are reset.
Rev. 3.00 Jan 11, 2005 page 606 of 1220
REJ09B0186-0300O